Cypress Semiconductor /psoc63 /SRSS /PWR_CTL

Current power mode of the device. LPACTIVE/LPSLEEP are implemented as firmware configuration of multiple registers and are reported here as ACTIVE/SLEEP, respectively. Note that this field cannot be read in all power modes on actual silicon.

0 (RESET): System is resetting.

1 (ACTIVE): At least one CPU is running.

2 (SLEEP): No CPUs are running. Peripherals may be running.

3 (DEEPSLEEP): Main high-frequency clock is off; low speed clocks are available. Communication interface clocks may be present.

Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)

0 (NO_SESSION): No debug session active

1 (SESSION_ACTIVE): Debug session is active. Power modes behave differently to keep the debug session active.

Indicates whether certain low power functions are ready. The low current circuits take longer to startup after POR/XRES/BOD/HIBERNATE wakeup than the normal mode circuits. HIBERNATE mode may be entered regardless of this bit. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready. If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP. When low power circuits are ready, device will automatically enter the originally requested mode. 1: Normal operation. DEEPSLEEP and low power circuits operate as requested in other registers.

Control the power mode of the reference current generator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: Current reference generator operates in normal mode. It works for vddd ramp rates of 100mV/us or less. 1: Current reference generator operates in low power mode. Response time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less.

Indicates that the voltage reference buffer is ready. Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1.

Disable the DeepSleep regulator. For ULP products, this is only legal when the ULP SISO-LC/SIMO-LC Buck supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: DeepSleep Regulator is on. 1: DeepSleep Regulator is off.

Disable the Retention regulator. For ULP products, this is only legal when the ULP SISO-LC/SIMO-LC Buck supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: Retention Regulator is on. 1: Retention Regulator is off.

Disable the Nwell regulator. For ULP products, this is only legal when the ULP SISO-LC/SIMO-LC Buck supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: Nwell Regulator is on. 1: Nwell Regulator is off.

Disable the linear Core Regulator. For ULP products, this is only legal when the ULP SISO-LC/SIMO-LC Buck supplies vccd, but there is no hardware protection for this case. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: Linear regulator is on. 1: Linear regulator is off.

Control the power mode of the ULP Linear Regulator. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: ULP Linear Regulator operates in normal mode. Internal current consumption is 50uA and load current capability is 50mA to 300mA, depending on the number of regulator modules present in the product. 1: ULP Linear Regulator operates in low power mode. Internal current consumption is 5uA and load current capability is 25mA. Firmware must ensure the current is kept within the limit.

Control the power mode of the ULP POR/BOD circuits. The value in this register is ignored and normal mode is used until LPM_READY==1. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: ULP POR/BOD circuits operate in normal mode. They work for vddd ramp rates of 100mV/us or less. 1: ULP POR/BOD circuits operate in low power mode. Response time is reduced to save current, and they work for vddd ramp rates of 10mV/us or less.

Control the power mode of the ULP Bandgap Voltage and Current References. This applies to voltage and current generation and is different than the reference voltage buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. When lower power mode is used, the Active Reference circuit can be disabled to reduce current. Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: ULP Active Bandgap Voltage and Current Reference operates in normal mode. They work for vddd ramp rates of 100mV/us or less. 1: ULP Active Bandgap Voltage and Current Reference operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less. The Active Reference may be disabled using ACT_REF_DIS=0.

Bypass level shifter inside the PLL. 0: Do not bypass the level shifter. This setting is ok for all operational modes and vccd target voltage. 1: Bypass the level shifter. This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal. Otherwise, it can result in clock degradation and static current.

Control the power mode of the 800mV voltage reference buffer. The value in this register is ignored and normal mode is used until LPM_READY==1. 0: ULP Voltage Reference Buffer operates in normal mode. They work for vddd ramp rates of 100mV/us or less. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 1: ULP Voltage Reference Buffer operates in low power mode. Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less.

Disable the 800mV voltage reference buffer. Firmware should only disable the buffer when there is no connected circuit that is using it. SRSS circuits that require it are the PLL and ECO. A particular product may have circuits outside the SRSS that use the buffer. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE.

Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference. When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready. This register is only reset by XRES/POR/BOD/OVP/HIBERNATE. 0: Active Reference is enabled 1: Active Reference is disabled

Indicates that the normal mode of the Active Reference is ready.